DAY60 In-Depth Analysis of Embedded Timers: Hands-on Practice from 51 MCU to i.MX6ULL EPIT GPT

In-Depth Analysis of Embedded Timers: Hands-on Practice from 51 MCU to i.MX6ULL EPIT & GPT

I. Prerequisite Basics: The “Heartbeat” of Timers – Clocks and Frequency Division/Multiplication

The essence of a timer is “counting known-frequency clock cycles,” so astable clock sourceand aflexible frequency adjustment mechanism(frequency division/multiplication) are prerequisites for accurate timer operation. Let’s clarify these core concepts first:

1.1 Clock Source: Crystal Oscillator (Xtal)

The crystal oscillator is the “source” of the entire system clock. Its working principle is: Quartz crystal is cut into a tuning-fork structure, and when voltage is applied, it produces stable mechanical oscillations, thereby outputting precise electrical signals (e.g., 8MHz, 24MHz, 12MHz).

• Features: Stable frequency, minimal error, the most critical clock source for embedded systems.
• Examples: 51 MCUs commonly use 11.0592MHz crystals, while i.MX6ULL development boards typically use 24MHz crystals (osc_clk).

1.2 Phase-Locked Loop (PLL): The Core of Low-Frequency Clock Multiplication

The low-frequency signal output by the crystal cannot meet the high-frequency demands of CPUs/peripherals, so PLL (Phase-Locked Loop) is used for frequency multiplication:

• Principle: Through phase-locking mechanisms, the input low-frequency clock signal is amplified into a high-frequency signal (e.g., i.MX6ULL’s PLL1 can multiply step_clk from 24MHz to 1056MHz).
• Key Note: Before configuring the PLL multiplication factor, the post-PLL division (e.g., divide-by-2) must be set first; otherwise, the ARM core may fail due to overclocking!

1.3 Frequency Divider (Prescale/PODF): Adapting High-Frequency Clocks

The high-frequency clock output by the PLL needs to be divided to match the operating frequencies of different peripherals:

• Principle: Reduces the high-frequency clock signal by a fixed ratio (e.g., division operation).
• i.MX6ULL Practical Configuration Example:
  • AHB_CLK_ROOT (132MHz): Select the clock source viaCBCMR[PRE_PERIPH_CLK_SEL], switch paths viaCBCDR[PERIPH_CLK_SEL], and set division viaCBCDR[AHB_PODF].
  • IPG_CLK_ROOT (66MHz): Obtained by dividing viaCBCDR[IPG_PODF].
  • PERCLK_CLK_ROOT (66MHz): Select the source viaCSCMR1[PERCLK_CLK_SEL]and divide viaCSCMR1[PERCLK_PODF].

1.4 Phase Fractional Divider (PFD): Flexible Frequency Adjustment

PFD is a more flexible frequency adjustment module than ordinary dividers, supporting “frequency multiplication” or “division” of output frequencies. It is mainly used in i.MX6ULL’s 528PLL (CCM_ANALOG_PFD_528n) and 480PLL (CCM_ANALOG_PFD_480n) to meet the clock requirements of different peripherals.

Commonly Confused Units

• Frequency Calculation:1MHz = 1000×1000 Hz(used for timer counting and clock frequencies).
• Storage Calculation:1MByte = 1024×1024 Byte(used for memory/Flash capacity calculations).

II. 51 MCU Timers: Hands-on Practice with Basic 8/16-bit Timers

The Timer1 and Timer2 in 51 MCUs are entry-level timers, primarily divided into “8-bit auto-reload” and “16-bit manual reload” modes. We’ll use the commonly employed 16-bit timer as an example to explain the principles and practical implementation.

2.1 Core Principles of 51 Timers

• Counting Target: Counts “machine cycles” (machine cycle = 12 / crystal frequency; e.g., 11.0592MHz crystal yields a machine cycle ≈ 1.085μs).
• 8-bit Auto-Reload: After counter overflow, the initial value is automatically reloaded from the preset reload register without manual intervention.
• 16-bit Manual Reload: After counter overflow, the THx/TLx initial values must be manually reset in the interrupt service function; otherwise, the next count starts from 0.

2.2 Hands-on: 1s Interrupt to Toggle LED (Timer0 Example)

Requirement

Implement a 1s timer interrupt using Timer0 (16-bit mode) on a 51 MCU, toggling the LED state in the interrupt service function.

Hardware Environment

• Crystal: 11.0592MHz.
• LED: Connected to P1.0, active-low.

Code Implementation

#include<reg51.h>// Define LED pinsbit LED=P1^0;// Define interrupt count variable (50ms × 20 = 1000ms)unsignedcharcnt=0;/** * @brief Timer0 Initialization: Configure 16-bit mode, 50ms timing */voidTimer0_Init(void){// 1. Configure timer mode: TMOD=0x01 (Timer0, 16-bit timer, counts only machine cycles)TMOD&=0xF0;// Clear Timer0 mode bitsTMOD|=0x01;// 2. Set initial count value: 11.0592MHz crystal, machine cycle ≈1.085μs, 50ms requires 46080 counts// 16-bit counter max value is 65536, initial value = 65536 - 46080 = 19456 = 0x4C00TH0=0x4C;// High 8 bitsTL0=0x00;// Low 8 bits// 3. Enable Timer0 interrupt and global interruptET0=1;// Enable Timer0 interruptEA=1;// Enable global interrupt// 4. Start Timer0TR0=1;}/** * @brief Timer0 Interrupt Service Function */voidTimer0_ISR(void)interrupt1{// Manual reload initial value (16-bit mode lacks auto-reload; must reset after overflow)TH0=0x4C;TL0=0x00;// Count 20 times = 50ms × 20 = 1000mscnt++;if(cnt>=20){cnt=0;LED=~LED;// Toggle LED state}}voidmain(void){Timer0_Init();// Initialize timerwhile(1);// Main loop idle, relies on interrupt handling}

Code Explanation

1. Mode Configuration:TMOD=0x01sets Timer0 to 16-bit timer mode, counting only machine cycles (not external pulses).
2. Initial Value Calculation: With an 11.0592MHz crystal, 50ms requires50ms / 1.085μs ≈ 46080counts, so the initial value = 65536 - 46080 = 0x4C00.
3. Interrupt Mechanism:ET0=1enables Timer0 interrupt,EA=1enables global interrupt; overflow triggersinterrupt 1(Timer0 interrupt vector).
4. 1s Implementation: Single timing of 50ms, accumulated to 1s viacntcounting 20 times, toggling the LED afterward.

3. i.MX6ULL Timers: EPIT & GPT Practical Guide

The i.MX6ULL, as an industrial-grade ARM Cortex-A7 chip, provides enhanced timers—EPIT (Enhanced Periodic Interrupt Timer) and GPT (General Purpose Timer)—far surpassing the basic timers of 51 microcontrollers.

3.1 EPIT (Enhanced Periodic Interrupt Timer)

EPIT is designed forperiodic interrupts, with core advantages likeauto-reloading initial countsandprecise periodic timing. Unlike the 51’s 16-bit timers, it eliminates manual reloading, making it ideal for LED toggling, timed data sampling, etc.

EPIT Core Principles

• Clock Source: Defaults to IPG_CLK_ROOT (66MHz), divisible for use.
• Counting Mode: Down-counting from a preset load value (LR register) to 0. Triggers an interrupt and auto-reloads LR, enabling cyclic counting.
• 1s Interrupt Calculation: With EPIT input clock at 1MHz (66MHz divided by 66), counting 1,000,000 times achieves 1s timing.

Demo: 1s Interrupt to Toggle LED

Hardware Setup

• i.MX6ULL dev board, LED connected to GPIO1_IO03.
• EPIT clock source: IPG_CLK_ROOT (66MHz).

Code (Bare-Metal Driver)

#include"imx6ull.h"// LED Init: GPIO1_IO03 as outputvoidLED_Init(void){// 1. Enable GPIO1 clockCCM->CCGR1|=(3<<26);// CG13 (GPIO1) = 11// 2. Configure GPIO1_IO03 as outputIOMUXC_SetPinMux(IOMUXC_GPIO1_IO03_GPIO1_IO03,0);IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO03_GPIO1_IO03,0x10B0);// 3. Set direction + initial state (OFF)GPIO1->GDIR|=(1<<3);GPIO1->DR|=(1<<3);}// Toggle LED statevoidLED_Toggle(void){GPIO1->DR^=(1<<3);}/** * @brief EPIT Init: 1s periodic interrupt */voidEPIT_Init(void){// 1. Enable EPIT1 clock (IPG_CLK_ROOT=66MHz)CCM->CCGR1|=(3<<20);// CG10 (EPIT1) = 11// 2. Reset EPIT1EPIT1->CR=(1<<1);// SWR=1 (reset)while(EPIT1->CR&(1<<1));// Wait for reset// 3. Configure EPIT1_CREPIT1->CR=0;EPIT1->CR|=(1<<24);// CLKSRC=1: IPG_CLK_ROOT (66MHz)EPIT1->CR|=(65<<4);// PRESCALAR=65: /66 → 1MHzEPIT1->CR|=(1<<3);// RLDPD=1: Sleep mode activeEPIT1->CR|=(1<<2);// IOVW=1: Override counterEPIT1->CR|=(1<<1);// ENMOD=1: Auto-reload LREPIT1->CR|=(1<<0);// EN=0 (disable until LR set)// 4. Set LR: 1MHz → 1s = 1,000,000 countsEPIT1->LR=1000000;// 5. Set CMPR: 0 (interrupt at 0)EPIT1->CMPR=0;// 6. Enable EPIT1 IRQGIC_EnableIRQ(EPIT1_IRQn);system_register_irqhandler(EPIT1_IRQn,(system_irq_handler_t)EPIT1_IRQHandler,NULL);// 7. Start EPIT1EPIT1->CR|=(1<<0);}/** * @brief EPIT1 IRQ Handler */voidEPIT1_IRQHandler(void){if(EPIT1->SR&(1<<0)){// Check IFLAGLED_Toggle();EPIT1->SR|=(1<<0);// Clear IFLAG}}intmain(void){LED_Init();EPIT_Init();while(1);return0;}

Code Breakdown

1. Clock Setup:CCM->CCGR1enables EPIT1, CR selects IPG_CLK_ROOT (66MHz) with /66 divider → 1MHz.
2. Counting:LR=1,000,000for 1s threshold.ENMOD=1enables auto-reload.
3. IRQ Handling: Toggles LED onSR[IFLAG]and clears the flag.

3.2 GPT (General Purpose Timer)

GPT is more versatile, supportingfree-run mode,input capture, andcompare output. Free-run mode is ideal for precise delays.

GPT Core Principles (Free-Run Mode)

• Free-Run: Counter increments from 0, wraps to 0 on overflow.
• Delay Logic: Record start countstart, loop untilcurrent - start≥ delay target.

Demo: Free-Run Mode for Precise Delays

Requirements

ImplementGPT_DelayUs(uint32_t us)(µs) andGPT_DelayMs(uint32_t ms)(ms) using GPT.

Code

#include"imx6ull.h"/** * @brief GPT Init: Free-run, IPG_CLK_ROOT (66MHz) */voidGPT_Init(void){// 1. Enable GPT1 clockCCM->CCGR1|=(3<<18);// CG9 (GPT1) = 11// 2. Reset GPT1GPT1->CR=(1<<15);// SWR=1 (reset)while(GPT1->CR&(1<<15));// 3. Configure GPT1_CRGPT1->CR=0;GPT1->CR|=(1<<1);// CLKSRC=1: IPG_CLK_ROOT (66MHz)GPT1->CR&=~(1<<0);// FRR=0: Free-run (wrap on overflow)GPT1->CR&=~(1<<2);// CLKEN=0: Disable until configured// 4. Set PR: /66 → 1MHz (1µs/count)GPT1->PR=65;// 5. Start GPT1GPT1->CR|=(1<<2);}/** * @brief Microsecond delay * @param us Delay in µs (0~4294967295) */voidGPT_DelayUs(uint32_tus){uint64_tstart=GPT1->CNT;uint64_ttarget=start+us;// Handle 32-bit overflowif(target>0xFFFFFFFF){while(GPT1->CNT<start);while(GPT1->CNT<(target-0xFFFFFFFF-1));}else{while(GPT1->CNT<target);}}/** * @brief Millisecond delay * @param ms Delay in ms (0~4294967295) */voidGPT_DelayMs(uint32_tms){for(uint32_ti=0;i<ms;i++){GPT_DelayUs(1000);// 1ms = 1000µs}}// Test: LED blink (1s delay)voidLED_Init(void){CCM->CCGR1|=(3<<26);IOMUXC_SetPinMux(IOMUXC_GPIO1_IO03_GPIO1_IO03,0);IOMUXC_SetPinConfig(IOMUXC_GPIO1_IO03_GPIO1_IO03,0x10B0);GPIO1->GDIR|=(1<<3);GPIO1->DR|=(1<<3);}intmain(void){LED_Init();GPT_Init();while(1){GPIO1->DR&=~(1<<3);// LED ONGPT_DelayMs(1000);GPIO1->DR|=(1<<3);// LED OFFGPT_DelayMs(1000);}return0;}

Code Analysis

1. Clock Configuration: GPT1 selects IPG_CLK_ROOT (66MHz), divides it by 66 to obtain a 1MHz clock (1μs/count), ensuring microsecond-level delay accuracy.
2. Free-Run Mode:FRR=0enables free-run mode, where the counter increments from 0 and automatically resets to 0 upon overflow.
3. Delay Logic:
   • Microsecond Delay: Records the initial count value, calculates the target count value (initial value + delay microseconds), and waits for the counter to reach the target.
   • Overflow Handling: The 32-bit counter has a maximum value of0xFFFFFFFF(~4294 seconds). If the target value exceeds this, it first waits for overflow before continuing the count.
   • Millisecond Delay: Iteratively calls the microsecond delay function (1ms = 1000μs).

IV. Summary and Extensions

4.1 Comparison of Timers Across Platforms

4.2 Practical Considerations

1. Clock Configuration is Key: Incorrect PLL/divider settings can lead to inaccurate timer counts or even system crashes.
2. Keep ISRs Concise: Avoid time-consuming operations in EPIT interrupt service routines to maintain timing precision.
3. Accurate Initial Value Calculation: Precisely calculate the divider and initial count based on clock frequency and timing requirements.

4.3 Expansion Directions

1. GPT Input Capture: Measure external pulse width/period (e.g., button debounce, ultrasonic ranging).
2. GPT Compare Output: Generate PWM waves (e.g., motor speed control, LED breathing effects).
3. EPIT Multitasking: Implement a simple task scheduler based on EPIT interrupts to manage multiple timed tasks.